The present patent application relates to a timing circuit for generation of trigger signals for a radar level gauging system. The present patent application further relates to a method for generation of trigger signals for a radar level gauging system. The invention can be used to generate a reference transmit clock and a swept-delay receive clock for sampling-type fluid level sensing radar systems.
Non-contact range measurement pulse-echo radar systems for fluid level sensing in tanks and vats typically consist of a transmitter which is arranged to radiate short duration radio frequency (RF) bursts via a highly directional antenna. After a delay a receiver is gated at a particular point in time. The timing of gating of the receiver is typically swept across a range of delays in a matter of milliseconds, such that a video output of the receiver can be provided as a scan like waveform. This waveform replicates occurring echoes on a real-time scale, corresponding to the physical distances represented by the echoes as the exact delay of a received echo pulse in relation to the transmitted pulse provides a measure of the distance to the reflecting object.
Highly accurate timing of the transmitted RF bursts and the gating of the receiver is necessary in order to be able to obtain high accuracy range information.
A precision digital pulse phase generator timing circuit is previously known through U.S. Pat. No. 5,563,605. This timing generator comprises a crystal oscillator connected to provide an output reference pulse. A resistor-capacitor combination is connected to provide a variable-delay output pulse from an input connected to the crystal oscillator. A phase monitor is connected to provide duty-cycle representations of the reference and variable-delay output pulse phase. An operational amplifier drives a control voltage to the resistor-capacitor combination according to currents integrated from the phase monitor and injected into summing junctions. A digital-to-analog converter injects a control current into the summing junctions according to an input digital control code. A servo equilibrium results that provides a phase delay of the variable-delay output pulse to the output reference pulse that linearly depends on the input digital control code.
However, the timing circuit previously known through U.S. Pat. No. 5,563,605, employs a NAND gate as a phase comparator in a delay locked loop configuration, which NAND gate must operate with sufficient clock timing difference to allow for the propagation of a sufficiently wide pulse through it. This presents a problem for radar circuits that must operate down to a zero range, such as for fluid level measurement in a tank, since the delay hereby introduced makes it virtually impossible to detect close range echoes. Furthermore, this previously known circuit has the disadvantage of having significant phase jitter or instability in the sample clock. This is a result of performance limitations of the high speed comparator required as part of the phase delay generator.
One object of the invention is to provide an improved timing circuit for generation of trigger signals for a radar level gauging system.
A further object of the present invention is to provide a precision timing circuit for generation of trigger signals for a radar level gauging system which does not rely on tolerances or matching of discrete components.
Another object of the present invention is to provide a precision timing circuit for generation of trigger signals for a radar level gauging system in which the relationship between the transmit clock and a swept-delay receive clock will remain the same, irrespective of external influences.
Briefly, a timing circuit embodiment of the present invention comprises a pulse-width modulator, having an input connected to a pulse-repetition-frequency generating oscillator. A monostable multivibrator, having an input connected to an output of the pulse-width modulator. First and second integrators connected to an output of the pulse-width modulator and the monostable multivibrator respectively. A voltage summation element, connected to an output of the first and second integrators respectively and at least one control signal input. A servo regulator providing a control loop between an output of the voltage summation element and a control port of the pulse-width modulator. A servo equilibrium results such that a reference clock output is provided at the output of the monostable multivibrator and a second clock output is provided at the output of the pulse-width modulator, where the phase delay of the of the second clock output to the reference clock output linearly depends on the control signal input.
A further object of the present invention is to provide an improved method for generation of trigger signals for a radar level gauging system.
Briefly, a method for generation of trigger signals for a radar level gauging system comprises the following steps. Providing a pulse-repetition-frequency clock pulse to a pulse width modulator. Using a first edge of an output pulse from the pulse width modulator to trigger a monostable multivibrator to output a fixed width pulse having one common edge with the first edge of the output pulse from the pulse width modulator. Obtaining average voltages related to the duty cycles of the output pulses from the pulse width modulator and the monostable multivibrator. Controlling the delay of the output pulse from the pulse width modulator with respect to the output pulse from the monostable multivibrator by regulating the average voltages.
An advantage of the circuit and method in accordance with the present invention compared to prior art circuits and methods is that both the initial phase and the variable phase or delay difference between the triggering edges of the output signals are independently and accurately regulated to definable values, without having to rely on tolerances or matching of discrete components, such as resistors or capacitors.
A further advantage of the circuit in accordance with the present invention is that relationship between the transmit clock and a swept-delay receive clock will remain the same, irrespective of external influences, such as ambient temperature, influencing the components thereof.